View AT25DF081A-MH-T_6724784.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? single 2.7v - 3.6v supply ? serial peripheral inte rface (spi) compatible ? supports spi modes 0 and 3 ? supports rapids operation ? supports dual-input prog ram and dual-output read ? very high operating frequencies ? 100mhz for rapids ? 85mhz for spi ? clock-to-output (t v ) of 5ns maximum ? flexible, optimized erase architecture for code + data storage applications ? uniform 4-kbyte block erase ? uniform 32-kbyte block erase ? uniform 64-kbyte block erase ? full chip erase ? individual sector protection with global protect/unprotect feature ? 16 sectors of 64-kbytes each ? hardware controlled locking of protected sectors via wp pin ? sector lockdown ? make any combination of 64-kbyte sectors permanently read-only ? 128-byte programmable otp security register ? flexible programming ? byte/page program (1- to 256-bytes) ? fast program and erase times ? 1.0ms typical page program (256 bytes) time ? 50ms typical 4-kbyte block erase time ? 250ms typical 32-kbyte block erase time ? 400ms typical 64-kbyte block erase time ? automatic checking and reporting of erase/program failures ? software controlled reset ? jedec standard manufacturer an d device id read methodology ? low power dissipation ? 5ma active read current (typical at 20mhz) ? 5a deep power-down current (typical) ? endurance: 100,000 program/erase cycles ? data retention: 20 years ? complies with full industrial temperature range ? industry standard green (pb/halide -free/rohs compliant) package options ? 8-lead soic (150-mil and 208-mil wide) ? 8-pad ultra thin dfn (5 x 6 x 0.6mm) 8-mbit 2.7v minimum serial peripheral interface serial flash memory atmel at25df081a 8715b?sflsh?8/10
2 8715b?sflsh?8/10 atmel at25df081a 1. description the atmel ? at25df081a is a serial interface flash memory dev ice designed for use in a wide variety of high-vol- ume consumer based applications in which program code is shadowed from flash memory into embedded or external ram for execution. the flexible erase architecture of the at25df081a, with its erase granularity as small as 4-kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage eeprom devices. the physical sectoring and the erase block sizes of the at25df081a have been optimized to meet the needs of today's code and data storage applications. by optimizing t he size of the physical se ctors and erase blocks, the memory space can be used much more efficiently. because certain code modules and data storage segments must reside by themselves in their own protected sector s, the wasted and unused memory space that occurs with large sectored and large block erase flash memory device s can be greatly reduced. this increased memory space efficiency allows additional code rout ines and data storage segments to be added while still ma intaining the same overall device density. the at25df081a also offers a sophisticated method for protecting individual sectors against erroneous or mali- cious program and erase operations. by providing the ability to individu ally protect and unprot ect sectors, a system can unprotect a specific sector to mo dify its contents while keeping the remaining sectors of the memory array securely protected. this is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. in addition to individual sector protection capabilities, the at25df081a incorporates global protect and global unprot ect features that allow the entire memory array to be either protected or unprotected all at once. this reduce s overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. to take code and data protection to the next level, th e at25df081a incorporates a sector lockdown mechanism that allows any combination of individual 64-kbyte sectors to be locked down and become permanently read-only. this addresses the need of certain secure applications that require portions of the flash memory array to be per- manently protected against malicious attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys, and routines. the device also contains a specialized otp (one-time pro- grammable) security register that can be used for pur poses such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. specifically designed for use in 3-volt systems, the at25df081a supports read, program, and erase operations with a supply voltage range of 2.7v to 3.6v. no separate voltage is required for programming and erasing.
3 8715b?sflsh?8/10 atmel at25df081a 2. pin descriptions and pinouts table 2-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in standby mode (not deep power- down mode), and the so pin will be in a high-impedance state. when the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the st andby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched in on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. - input si (sio) serial input (serial input/output): the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched in on the rising edge of sck. with the dual-output read arra y command, the si pin becomes an output pin (sio) to allow two bits of data (on the so and sio pins) to be clocked out on every falling edge of sck. to maintain consistency with spi nomenclature, t he sio pin will be referenced as si throughout the document with exception to sections d ealing with the dual-output read array command in which it will be referenced as sio. data present on the si pin will be ignore d whenever the device is deselected (cs is deasserted). - input/output so (soi) serial output (serial output/input): the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. with the dual-input byte/page program command, the so pin becomes an input pin (soi) to allow two bits of data (on the soi and si pins) to be clocked in on every rising edge of sck. to maintain consistency with spi nomenclature, the soi pin will be referenced as so throughout the document with exception to se ctions dealing with the dual-input byte/page program command in which it will be referenced as soi. the so pin will be in a high-impedance state whenever the device is deselected (cs is deasserted). - output/input wp write protect: the wp pin controls the hardware locking feature of the device. please refer to ?protection commands and features? on page 17 for more details on protection features and the wp pin. the wp pin is internally pulled-high and may be le ft floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input hold hold: the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses se rial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. please refer to ?hold? on page 41 for additional details on the hold operation. the hold pin is internally pulled-high and may be left floating if the hold function will not be used. however, it is recommended that the hold pin also be externally connected to v cc whenever possible. low input
4 8715b?sflsh?8/10 atmel at25df081a 3. block diagram figure 3-1. block diagram v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. -power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. -power table 2-1. pin descriptions (continued) symbol name and function asserted state type figure 2-1. 8-soic (top view) figure 2-2. 8-udfn (top view) cs so (soi) wp gnd 1 2 3 4 8 7 6 5 vcc hold sck si (sio) cs so (soi) wp gnd 1 2 3 4 8 7 6 5 vcc hold sck si (sio) flash memory array y-gating cs sck so (soi) si (sio) y-decoder address latch x-decoder i/o buffers and latches control and protection logic sram data buffer wp interface control and logic hold
5 8715b?sflsh?8/10 atmel at25df081a 4. memory array to provide the greatest flexibility, the memory array of the atmel ? at25df081a can be erased in four levels of granularity including a full chip erase. in addition, the ar ray has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. the size of the physical sectors is optimized for both code and data storage app lications, allowing both code and data segments to reside in their own isolated regions. the memory architecture diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. figure 4-1. memory architecture diagram internal s ectorin g fo r 64kb 3 2kb 4kb 1-256 byte s ector protection block era s e block era s e block era s epa g e pro g ram function (d 8 h command) (52h command) (20h command) (02h command) 4kb 0fffffh ? 0ff000h 256 byte s 0fffffh ? 0fff00h 4kb 0fefffh ? 0fe000h 256 byte s 0ffeffh ? 0ffe00h 4kb 0fdfffh ? 0fd000h 256 byte s 0ffdffh ? 0ffd00h 4kb 0fcfffh ? 0fc000h 256 byte s 0ffcffh ? 0ffc00h 4kb 0fbfffh ? 0fb000h 256 byte s 0ffbffh ? 0ffb00h 4kb 0fafffh ? 0fa000h 256 byte s 0ffaffh ? 0ffa00h 4kb 0f9fffh ? 0f9000h 256 byte s 0ff9ffh ? 0ff900h 4kb 0f 8 fffh ? 0f 8 000h 256 byte s 0ff 8 ffh ? 0ff 8 00h 4kb 0f7fffh ? 0f7000h 256 byte s 0ff7ffh ? 0ff700h 4kb 0f6fffh ? 0f6000h 256 byte s 0ff6ffh ? 0ff600h 4kb 0f5fffh ? 0f5000h 256 byte s 0ff5ffh ? 0ff500h 4kb 0f4fffh ? 0f4000h 256 byte s 0ff4ffh ? 0ff400h 4kb 0f 3 fffh ? 0f 3 000h 256 byte s 0ff 3 ffh ? 0ff 3 00h 4kb 0f2fffh ? 0f2000h 256 byte s 0ff2ffh ? 0ff200h 4kb 0f1fffh ? 0f1000h 256 byte s 0ff1ffh ? 0ff100h 4kb 0f0fffh ? 0f0000h 256 byte s 0ff0ffh ? 0ff000h 4kb 0effffh ? 0ef000h 256 byte s 0fefffh ? 0fef00h 4kb 0eefffh ? 0ee000h 256 byte s 0feeffh ? 0fee00h 4kb 0edfffh ? 0ed000h 256 byte s 0fedffh ? 0fed00h 4kb 0ecfffh ? 0ec000h 256 byte s 0fecffh ? 0fec00h 4kb 0ebfffh ? 0eb000h 256 byte s 0febffh ? 0feb00h 4kb 0eafffh ? 0ea000h 256 byte s 0feaffh ? 0fea00h 4kb 0e9fffh ? 0e9000h 256 byte s 0fe9ffh ? 0fe900h 4kb 0e 8 fffh ? 0e 8 000h 256 byte s 0fe 8 ffh ? 0fe 8 00h 4kb 0e7fffh ? 0e7000h 4kb 0e6fffh ? 0e6000h 4kb 0e5fffh ? 0e5000h 4kb 0e4fffh ? 0e4000h 256 byte s 0017ffh ? 001700h 4kb 0e 3 fffh ? 0e 3 000h 256 byte s 0016ffh ? 001600h 4kb 0e2fffh ? 0e2000h 256 byte s 0015ffh ? 001500h 4kb 0e1fffh ? 0e1000h 256 byte s 0014ffh ? 001400h 4kb 0e0fffh ? 0e0000h 256 byte s 001 3 ffh ? 001 3 00h 256 byte s 0012ffh ? 001200h 256 byte s 0011ffh ? 001100h 256 byte s 0010ffh ? 001000h 4kb 00ffffh ? 00f000h 256 byte s 000fffh ? 000f00h 4kb 00efffh ? 00e000h 256 byte s 000effh ? 000e00h 4kb 00dfffh ? 00d000h 256 byte s 000dffh ? 000d00h 4kb 00cfffh ? 00c000h 256 byte s 000cffh ? 000c00h 4kb 00bfffh ? 00b000h 256 byte s 000bffh ? 000b00h 4kb 00afffh ? 00a000h 256 byte s 000affh ? 000a00h 4kb 009fffh ? 009000h 256 byte s 0009ffh ? 000900h 4kb 00 8 fffh ? 00 8 000h 256 byte s 000 8 ffh ? 000 8 00h 4kb 007fffh ? 007000h 256 byte s 0007ffh ? 000700h 4kb 006fffh ? 006000h 256 byte s 0006ffh ? 000600h 4kb 005fffh ? 005000h 256 byte s 0005ffh ? 000500h 4kb 004fffh ? 004000h 256 byte s 0004ffh ? 000400h 4kb 00 3 fffh ? 00 3 000h 256 byte s 000 3 ffh ? 000 3 00h 4kb 002fffh ? 002000h 256 byte s 0002ffh ? 000200h 4kb 001fffh ? 001000h 256 byte s 0001ffh ? 000100h 4kb 000fffh ? 000000h 256 byte s 0000ffh ? 000000h ? ? ? 64kb block era s e detail pa g e pro g ram detail pa g e addre ss block addre ss 3 2kb 3 2kb 64kb ( s ector 0) ran g e ? ? ? ? ? ? ran g e 3 2kb 3 2kb ? ? ? ? ? ? 64kb ( s ector 15) 64kb 3 2kb 3 2kb 64kb ( s ector 14) 64kb
6 8715b?sflsh?8/10 atmel at25df081a 5. device operation the atmel ? at25df081a is controlled by a set of instructions that are sent from a host controller, commonly referred to as the spi master. the spi master communicates with the at25df081a via the spi bus which is com- prised of four signal lines: chip select (cs ), serial clock (sck), serial input (si), and serial output (so). the at25df081a features a dual-input program mode in which the so pin becomes an input. similarly, the device also features a dual-output read mode in which the si pin becomes an output. in the dual-input byte/page pro- gram command description, the so pin will be referred to as the soi (serial output/input) pin, and in the dual- output read array command, the si pin will be re ferenced as the sio (s erial input/output) pin. the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the at25df081a supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the in active state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, da ta is always latched in on the rising edge of sck and always output on t he falling edge of sck. figure 5-1. spi mode 0 and 3 6. commands and addressing a valid instruction or operation must always be started by first asserting the cs pin. after the cs pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruc- tion dependent information such as address and data bytes would then be clocked out by the host controller. all opcode, address, and data bytes are transferred with the most -significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not supported by the at25df081a will be ignored by the device and no operation will be started. the device will continue to ignore any da ta presented on the si pin until the start of the next operation (cs pin being deasserted and then reasserted). in addition, if the cs pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of three bytes of information to be sent, representing address bits a23-a0. since the upper address limit of the at25df081a memory array is 0fffffh, address bits a23-a20 are always ignored by the device. sck cs si so msb lsb msb lsb
7 8715b?sflsh?8/10 atmel at25df081a table 6-1. command listing command opcode clock frequency address bytes dummy bytes data bytes read commands read array 1bh 0001 1011 up to 100mhz 3 2 1+ 0bh 0000 1011 up to 85mhz 3 1 1+ 03h 0000 0011 up to 50mhz 3 0 1+ dual-output read array 3bh 0011 1011 up to 85mhz 3 1 1+ program and erase commands block erase (4 kbytes) 20h 0010 0000 up to 100mhz 3 0 0 block erase (32 kbytes) 52h 0101 0010 up to 100mhz 3 0 0 block erase (64 kbytes) d8h 1101 1000 up to 100mhz 3 0 0 chip erase 60h 0110 0000 up to 100mhz 0 0 0 c7h 1100 0111 up to 100mhz 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 up to 100mhz 3 0 1+ dual-input byte/page program (1 to 256 bytes) a2h 1010 0010 up to 100mhz 3 0 1+ protection commands write enable 06h 0000 0110 up to 100mhz 0 0 0 write disable 04h 0000 0100 up to 100mhz 0 0 0 protect sector 36h 0011 0110 up to 100mhz 3 0 0 unprotect sector 39h 0011 1001 up to 100mhz 3 0 0 global protect/unprotect use write st atus register byte 1 command read sector protection registers 3ch 0011 1100 up to 100mhz 3 0 1+ security commands sector lockdown 33h 0011 0011 up to 100mhz 3 0 1 freeze sector lockdown state 34h 0011 0100 up to 100mhz 3 0 1 read sector lockdown registers 35h 0011 0101 up to 100mhz 3 0 1+ program otp security register 9bh 1001 1011 up to 100mhz 3 0 1+ read otp security register 77h 0111 0111 up to 100mhz 3 2 1+ status register commands read status register 05h 0000 0101 up to 100mhz 0 0 1+ write status register byte 1 01h 0000 0001 up to 100mhz 0 0 1 write status register byte 2 31h 0011 0001 up to 100mhz 0 0 1 miscellaneous commands reset f0h 1111 0000 up to 100mhz 0 0 1 read manufacturer and device id 9fh 1001 1111 up to 85mhz 0 0 1 to 4 deep power-down b9h 1011 1001 up to 100mhz 0 0 0 resume from deep power-down abh 1010 1011 up to 100mhz 0 0 0
8 8715b?sflsh?8/10 atmel at25df081a 7. read commands 7.1 read array the read array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. the device incorporates an internal address counter that automatically increments on every clock cycle. three opcodes (1bh, 0bh, and 03h) can be used for the read array command. the use of each opcode depends on the maximum clock frequency that will be used to r ead data from the device. the 0bh opcode can be used at any clock frequency up to t he maximum specified by f clk , and the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . the 1bh opcode allows the highest read performance pos- sible and can be used at any clock frequen cy up to the maximum specified by f max ; however, use of the 1bh opcode at clock frequencies above f clk should be reserved to systems employing the atmel rapids tm protocol. to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (1bh, 0bh, or 03h) must be clocked into the devi ce. after the opcode has been clocke d in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode is used for the read array operation. if the 1bh opcode is used, then two dummy bytes must be clocked into the device after the three address bytes. if the 0bh opcode is used, then a single dummy byte must be clocked in after the address bytes. after the three address bytes (and the dummy bytes or byte if using opcodes 1bh or 0bh) have been clocked in, additional clock cycles will result in da ta being output on the so pin. the data is always output with the msb of a byte first. when the last byte (0ff fffh) of the memory array has been re ad, the device will continue reading back at the beginning of the array (000000h) . no delays will be incurred when wrappi ng around from th e end of the array to the beginning of the array. deasserting the cs pin will terminate the read operat ion and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-1. read array ? 1bh opcode sck cs si so msb msb 23 1 0 00011011 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 50 51 49 52 55 56 54 53 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care msb xxxxxxx x don't care data byte 1 high-impedance
9 8715b?sflsh?8/10 atmel at25df081a figure 7-2. read array ? 0bh opcode figure 7-3. read array ? 03h opcode sck cs si so msb msb 23 1 0 00001011 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte 1 high-impedance
10 8715b?sflsh?8/10 atmel at25df081a 7.2 dual-output read array the dual-output read array command is similar to the standard read array command and can be used to sequentially read a continuous stream of data from the devi ce by simply providing the clock signal once the initial starting address has been specified. unlike the standard read array command, however, the dual-output read array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one. the dual-output read array command can be used at any clock frequency up to the maximum specified by f rddo . to perform the dual-output read array operation, the cs pin must first be asserted and the opcode of 3bh must be clocked into the device. after the opcode has been cl ocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, a single dummy byte must also be clocked into the device. after the three address bytes and the dummy byte have been clocked in, addit ional clock cycles will result in data being output on both the so and sio pins. the data is always output with the msb of a byte first, and the msb is always output on the so pin. during the first clock cycle, bit seven of the first data byte will be output on the so pin while bit six of the same data byte will be output on the sio pin. during the next clock cycle, bits five and four of the first data byte will be output on the so and sio pins, respectively . the sequence continues with each byte of data being output after every four clock cycles. when the last byte (0fffffh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrap- ping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read oper ation and put the so and sio pi ns into a high -impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-4. dual-output read array sck cs sio so msb msb 23 1 0 00111011 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa aa msb xxxxxxxx msb msb msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address bits a23-a0 don't care output data byte 1 output data byte 2 high-impedance
11 8715b?sflsh?8/10 atmel at25df081a 8. program and erase commands 8.1 byte/page program the byte/page program command allows anywhere from a single byte of data to 256-bytes of data to be pro- grammed into previously erased memory locations. an eras ed memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 17 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte/page program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can t hen be clocked into the device and will be stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on an even 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situa- tion, any data that is s ent to the device that goes beyond the e nd of the page will wr ap around back to the beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 0000 01h through 0000fdh) will not be programmed and will remain in t he erased state (f fh). in addi- tion, if more than 256-bytes of data are sent to the device, then only the la st 256-bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data st ored in the internal buff er and program it into the appropriate memory array locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 256-bytes of data were sent to the device, then the remaining bytes within the page will not be progr ammed and will remain in the eras ed state (ffh). the programming of the da ta bytes is inter- nally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundarie s (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. in addition, if the address specified by a23-a0 points to a memory location within a sector that is in the protected state (see ?protect sector? on page 19 ) or locked down (see ?sector lockdown? on page 25 ), then the byte/page program command will not be executed, and the device will retu rn to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected or locked down. while the device is programm ing, the status register ca n be read and will indicate th at the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent programming algor ithm that can detect when a byte location fails to pro- gram properly. if a programming error arises, it will be indicated by the epe bit in the status register.
12 8715b?sflsh?8/10 atmel at25df081a figure 8-1. byte program figure 8-2. page program sck cs si so msb msb 23 1 0 00000010 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aaaa aaa a a msb ddddddd d address bits a23-a0 data in sck cs si so msb msb 23 1 0 00000010 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n
13 8715b?sflsh?8/10 atmel at25df081a 8.2 dual-input byte/page program the dual-input byte/page program command is similar to the standard byte/page program command and can be used to program anywhere from a single byte of data up to 256-bytes of data into previously erased memory loca- tions. unlike the standard byte/page program command, however, the dual-input byte/page program command allows two bits of data to be clocked into the device on every clock cycle rather than just one. before the dual-input byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 17 ) to set the write enable latch (wel) bit of the sta- tus register to a logical ?1? state. to perform a dual-input byte/page program command, an opcode of a2h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have be en clocked in, data can then be clocked into the device two bits at a time on both the soi and si pins. the data is always input with the msb of a byte first, and the msb is always input on the soi pin. during the first clock cycle, bit seven of the first data byte would be input on the soi pin while bit six of the same data byte would be input on the si pin. during the next clock cycle, bits five and four of the first data byte would be input on the soi and si pins, respectively. the sequence would continue with each byte of data being input after every four clock cycles. like the standard byte/page program command, all data clocked into the device is stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on an even 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situa- tion, any data that is s ent to the device that goes beyond the e nd of the page will wr ap around back to the beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 0000 01h through 0000fdh) will not be programmed and will remain in t he erased state (f fh). in addi- tion, if more than 256-bytes of data are sent to the device, then only the la st 256-bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data st ored in the internal buff er and program it into the appropriate memory array locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 256-bytes of data were sent to the device, then the remaining bytes within the page will not be progr ammed and will remain in the eras ed state (ffh). the programming of the da ta bytes is inter- nally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundarie s (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. in addition, if the address specified by a23-a0 points to a memory location within a sector that is in the protected state (see ?protect sector? on page 19 ) or locked down (see ?sector lockdown? on page 25 ), then the byte/page program command will not be executed, and the device will retu rn to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected or locked down. while the device is programm ing, the status register ca n be read and will indicate th at the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent programming algor ithm that can detect when a byte location fails to pro- gram properly. if a programming error arises, it will be indicated by the epe bit in the status register.
14 8715b?sflsh?8/10 atmel at25df081a figure 8-3. dual-input byte program figure 8-4. dual-input page program sck cs si soi msb msb 23 1 0 10100010 67 5 41011 9 812 3335 34 31 32 29 30 opcode aaaa aaa a a address bits a23-a0 msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 input data byte high-impedance sck cs si soi msb msb 23 1 0 10100010 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode aaaa aaa a a msb msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address bits a23-a0 input data byte 1 msb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 input data byte n input data byte 2 high-impedance
15 8715b?sflsh?8/10 atmel at25df081a 8.3 block erase a block of 4-, 32-, or 64-kbytes can be erased (all bits set to the logical ?1? state) in a single operation by using one of three different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is used for a 32-kbyte erase, and an opcode of d8h is used for a 64-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. to perform a block erase, the cs pin must first be asserted and the appropriate opcode (20h, 52h, or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the devi ce will erase the appropriate block. the erasing of the block is internally self -timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. therefore, for a 4-kbyte erase, address bits a11-a0 will be ignored by the device and their values can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14-a0 will be ignored, and for a 64-kbyte erase, address bits a15-a0 will be ig nored by the device. despite the lowe r order address bits not being decoded by the device, the complete thr ee address bytes must still be cloc ked into the dev ice before the cs pin is deas- serted, and the cs pin must be deasserted on an even byte boundar y (multiples of eight bits); otherwise, the device will abort the oper ation and no erase opera tion will be performed. if the address specified by a23-a0 points to a memory loca tion within a sector that is in the protected or locked down state, then the block erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent, the cs pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected or locked down. while the device is executing a successful erase cycle, t he status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t blke time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be re set back to the logical ?0? state. the device also incorporates an intelligen t erase algorithm that can detect when a byte location fails to erase prop- erly. if an erase error occurs , it will be indicated by the epe bit in the status register. figure 8-5. block erase sck cs si so msb msb 23 1 0 cccccccc 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
16 8715b?sflsh?8/10 atmel at25df081a 8.4 chip erase the entire memory array can be erased in a single operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. two opcodes, 60h and c7h, can be used for the chip erase command. there is no difference in device functional- ity when utilizing the two opcodes, so t hey can be used interchangeably. to perform a chip erase, one of the two opcodes (60h or c7h) must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the devic e, and any data clocked in after th e opcode will be ignored. when the cs pin is deasserted, the device will erase the entire memory a rray. the erasing of the device is internally self-timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no eras e will be performed. in addition, if any sector of the memory array is in the protected or locked do wn state, then the chip erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the sta- tus register will be reset back to the logical ?0? state if the cs pin is deasserted on uneven byte boundaries or if a sector is in the protected or locked down state. while the device is executing a successf ul erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t chpe time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorpor ates an intelligent erase algorithm that can detect when a byte location fails to erase prop- erly. if an erase error occurs , it will be indicated by the epe bit in the status register. figure 8-6. chip erase sck cs si so msb 23 1 0 cccccccc 67 5 4 opcode high-impedance
17 8715b?sflsh?8/10 atmel at25df081a 9. protection commands and features 9.1 write enable the write enable command is used to set the write enable latch (wel) bit in the status register to a logical ?1? state. the wel bit must be set before a byte/page program, erase, protect sector, unprotect sector, sector lock- down, freeze sector lockdown state, program otp security register, or write status register command can be executed. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. if the wel bit in the status register is not set prior to the issuance of one of thes e commands, then the comma nd will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address bytes need to be clocked into the device, and any dat a clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the com- plete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (m ultiples of eight bits); otherwise, the devi ce will abort the operation and the state of the wel bit will not change. figure 9-1. write enable sck cs si so msb 23 1 0 00000110 67 5 4 opcode high-impedance
18 8715b?sflsh?8/10 atmel at25df081a 9.2 write disable the write disable command is used to reset the write enable latch (wel) bit in the status register to the logical "0" state. with the wel bit reset, all byte/page program , erase, protect sector, unprotect sector, sector lock- down, freeze sector lockdown state, program otp security register, and write status register commands will not be executed. other conditions can al so cause the wel bit to be reset; for more details, refer to the wel bit section of the status register description. to issue the write disable command, the cs pin must first be asserted and the opcode of 04h must be clocked into the device. no address bytes need to be clocked into the device, and an y data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deas- serted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-2. write disable sck cs si so msb 23 1 0 00000100 67 5 4 opcode high-impedance
19 8715b?sflsh?8/10 atmel at25df081a 9.3 protect sector every physical 64-kbyte sector of the device has a corres ponding single-bit sector protection register that is used to control the software pr otection of a sector. upon de vice power-up, each sector pr otection register will default to the logical ?1? state indicating that all sectors are protected and cannot be programmed or erased. issuing the protect sector command to a particul ar sector address will set the corresponding sector protection register to the logical ?1? state. the following table outlines the two states of the sector protection registers. before the protect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the protect sector command, the cs pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designat- ing any address within the se ctor to be protecte d. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the sector protection register corresponding to the physical sector addressed by a23- a0 will be set to the logical ?1? state, and the sector itself will then be protec ted from program a nd erase operations. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abo rt the opera- tion. when the device aborts the protect sector operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous protecting or unprotecting of sectors, the sector protection regis- ters can themselves be locked from updates by using the sprl (sector protection registers locked) bit of the status register (please refer to the status register descrip tion for more details). if the sector protection registers are locked, then any attempts to issue the protect sector command will be ignored, and the device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-3. protect sector table 9-1. sector protection register values value sector protection status 0 sector is unprotected and can be programmed and erased. 1 sector is protected and cannot be programm ed or erased. this is the default state. sck cs si so msb msb 23 1 0 00110110 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
20 8715b?sflsh?8/10 atmel at25df081a 9.4 unprotect sector issuing the unprotect sector command to a particular sector address will reset the corresponding sector protec- tion register to the logical ?0? state (see table 9-1 for sector protection register values). every physical sector of the device has a corresponding single-bit sector protection register that is used to control the software protection of a sector. before the unprotect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a l ogical ?1?. to issue the unprotect sector command, the cs pin must first be asserted and the opcode of 39h must be clocked into the device. after the opcode has been clocked in, the three address bytes designating any address within the sector to be unprotected must be clocked in. any additional data clocked into the device after the address bytes will be ignored. when the cs pin is deas- serted, the sector protection register corresponding to the sector addressed by a23-a0 will be reset to the logical ?0? state, and the sector itself will be unprotected. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the opera- tion, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking or unlocking of sectors, the sector protection registers can themselves be locked from updates by using the sprl (sector protection registers locked) bit of the status register (please refer to the status register description for more details). if the sector protection registers are locked, then any attempts to issue the unprotect sector command will be ignored, and the device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-4. unprotect sector sck cs si so msb msb 23 1 0 00111001 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
21 8715b?sflsh?8/10 atmel at25df081a 9.5 global protect/unprotect the global protect and global unprotect features can work in conjunction with the protect sector and unprotect sector functions. for example, a system can globally prot ect the entire memory array and then use the unprotect sector command to individually unprotect certain sectors an d individually reprotect them later by using the protect sector command. likewise, a system can globally unprotec t the entire memory array and then individually protect certain sectors as needed. performing a global protect or global unprotect is accomplished by writing a certain combination of data to the status register using the write st atus register byte 1 command (see ?write status register byte 1? on page 35 for command execution details). the write status register command is also used to modify the sprl (sector pro- tection registers locked) bit to control hardware and software locking. to perform a global protect, the appropriate wp pin and sprl conditions must be met, and the system must write a logical ?1? to bits five, four, three, and two of the first byte of the status register. conversely, to perform a global unprotect, the same wp and sprl conditions must be met but the system must write a logical ?0? to bits five, four, three, and two of the first byte of the status register. table 9-2 details the conditions necessary for a global pro- tect or global unprotect to be performed. table 9-2. valid sprl and global protect/unprotect conditions wp state current sprl value new write status register byte 1 data protection operation new sprl value bit 7 6 5 4 3 2 1 0 00 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x global unprotect ? all sector pr otection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 global unprotect ? all sector pr otection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1 0 1 x x x x x x x x no change to the current protection level. all sect ors currently protected will remain protected and all sectors currently unprotec ted will remain unprotected. the sector protection registers are har d-locked and cannot be changed when the wp pin is low and the current state of sprl is 1. therefor e, a global protect/unprot ect will not occur. in addition, the sprl bit cannot be changed (the wp pin must be high in order to change sprl back to a 0). 10 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x global unprotect ? all sector pr otection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 global unprotect ? all sector pr otection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1
22 8715b?sflsh?8/10 atmel at25df081a essentially, if the sprl bit of the status register is in the logical ?0? state (sector protection registers are not locked), then writing a 00h to the fi rst byte of the status register will pe rform a global unpr otect without changing the state of the sprl bit. simila rly, writing a 7fh to the firs t byte of the status register will perform a global protect and keep the sprl bit in the logical ?0? state. the sprl bit can, of course, be changed to a logical ?1? by writing an ffh if software-locking or hardware-locking is desired along with the global protect. if the desire is to only change the sprl bit without perfor ming a global protect or global unprotect, then the sys- tem can simply write a 0fh to the first byte of the status register to change the sprl bit from a logical ?1? to a logical ?0? provided the wp pin is deasserted. likewise, the system can write an f0h to change the sprl bit from a logical ?0? to a logical ?1? without a ffecting the current sector protection status (no chan ges will be made to the sector protection registers). when writing to the first byte of the st atus register, bits five, four, three, and two will not actually be modified but will be decoded by the device for the pu rposes of the global protect and global unprotect functi ons. only bit seven, the sprl bit, will ac tually be modified. t herefore, when reading the first byte of the status register, bits five, four, three, and two will not reflec t the values written to them but will in stead indicate the status of the wp pin and the sector protection status. please refer to ?read status register? on page 31 and table 11-1 on page 31 for details on the status register format and what values can be read for bits five, four, three, and two. 11 0 x 0 0 0 0 x x 0 x 0 0 0 1 x x 0 x 1 1 1 0 x x 0 x 1 1 1 1 x x 1 x 0 0 0 0 x x 1 x 0 0 0 1 x x 1 x 1 1 1 0 x x 1 x 1 1 1 1 x x no change to the current protection level. all sectors currently pr otected will remain protected, and all sectors currently unprotected will remain unprotected. the sector protection registers are soft-locked and cannot be changed when the current state of sprl is 1. therefore, a global protect/unprot ect will not occur. however, the sprl bit can be changed back to a 0 from a 1 since the wp pin is high. to perform a global protect/unprot ect, the write status register command must be issued again after the sprl bit has been changed from a 1 to a 0. 0 0 0 0 0 1 1 1 1 1 table 9-2. valid sprl and global protect/unprotect conditions (continued) wp state current sprl value new write status register byte 1 data protection operation new sprl value bit 7 6 5 4 3 2 1 0
23 8715b?sflsh?8/10 atmel at25df081a 9.6 read sector pr otection registers the sector protection registers can be read to determine t he current software protection status of each sector. reading the sect or protection registers, however, will not determi ne the status of the wp pin. to read the sector protection register for a particular sector, the cs pin must first be asserted and the opcode of 3ch must be clocked in. once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. a fter the last address byte has been cl ocked in, the device will begin output- ting data on the so pin during ever y subsequent clock cycle. the data being output will be a repeating byte of either ffh or 00h to denote the value of the appropriate sector protection register. at clock frequencies above f clk , the first byte of da ta output will not be va lid. therefore, if operating at clock fre- quencies above f clk , at least two bytes of data must be clocked out from the device in order to determine the correct status of the appropriate sector protection register. deasserting the cs pin will terminate the read operation and put t he so pin into a high-im pedance stat e. the cs pin can be deasserted at any time and does not require that a full byte of data be read. in addition to reading the individual sector protection regist ers, the software protection status (swp) bits in the status register can be read to determine if all, some, or none of the sectors are software protected (refer to ?read status register? on page 31 for more details). figure 9-5. read sector protection register table 9-3. read sector protection register ? output data output data sector protection register value 00h sector protection register va lue is 0 (sector is unprotected) ffh sector protection register va lue is 1 (sector is protected) sck cs si so msb msb 23 1 0 00111100 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte high-impedance
24 8715b?sflsh?8/10 atmel at25df081a 9.7 protected states and the write protect (wp ) pin the wp pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown status of the memory array. instead, the wp pin, in conjunction with the sp rl (sector protection registers locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met-the wp pin must be asserted and the sprl bit must be in the log- ical ?1? state. when hardware locking is active, the sector protection registers are locked and the sprl bit itself is also locked. therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. these states cannot be changed as long as hardware locking is active, so the pro- tect sector, unprotect sector, and write status regist er commands will be ignored. in order to modify the protection status of a sector, the wp pin must first be deasserted, and the sprl bit in the status register must be reset back to the logical ?0? state using the write status register command. when resetting the sprl bit back to a logical ?0?, it is not possible to perform a global protect or global unprotect at the same time since the sector pro- tection registers remain soft-locked until after the write status register command has been executed. if the wp pin is permanently connected to gnd, then once the sprl bit is set to a logical ?1?, the only way to reset the bit back to the logical ?0? state is to power-cycle the device. this allows a system to power-up with all sectors software protected but not hardware locked. therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the sprl bit in the status register. when the wp pin is deasserted, or if the wp pin is permanently connected to v cc , the sprl bit in the status reg- ister can still be set to a logical ?1? to lock the sector protection registers. this provides a software locking ability to prevent erroneous protect sector or unprotect sector commands from being processed. when changing the sprl bit to a logical ?1? from a logical ?0?, it is also poss ible to perform a global protect or global unprotect at the same time by writing the appropriate values into bits five, four, three, and two of the first byte of the status register. tables 9-4 and 9-5 detail the various protection and locking states of the device. note: 1. ?n? represents a sector number table 9-4. sector protection register states wp sector protection register n (1) sector n (1) x (don't care) 0 unprotected 1protected table 9-5. hardware and software locking wp sprl locking sprl change allowed sector protection registers 0 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands. global prot ect and unprotect can also be performed. 01 hardware locked locked locked in current state. pr otect and unprotect sector commands will be ignored. gl obal protect and unprotect cannot be performed. 1 0 can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands. global prot ect and unprotect can also be performed. 11 software locked can be modified from 1 to 0 locked in current state. pr otect and unprotect sector commands will be ignored. gl obal protect and unprotect cannot be performed.
25 8715b?sflsh?8/10 atmel at25df081a 10. security commands 10.1 sector lockdown certain applications require that portions of the flash memory array be permanently protected against malicious attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys, and routines. to address these applications, the device incorporates a sector lockdown mechanism that allows any combination of individual 64-kbyte sectors to be permanently locked so that they become read only. once a sector is locked down, it can never be erased or programmed again, and it can never be unlocked from the locked down state. each 64-kbyte physical sector has a corresponding single-bit sector lockdown register that is used to control the lockdown status of that sect or. these registers ar e nonvolatile and will retain their state even after a device power- cycle or reset operation. the following table outlines the two states of the sector lockdown registers. issuing the sector lockdown command to a particular sector address will se t the corresponding sector lockdown register to the logical ?1? state. each sector lockdown register can only be set once; therefore, once set to the logical ?1? state, a sector lockdown register cannot be reset back to the logical ?0? state. before the sector lockdown command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logi cal ?1?. in addition, the sector lockdown enabled (sle) bit in the status register must have also been previously set to the logical ?1? state by using the write status register byte 2 command (see ?write status register byte 2? on page 36 ). to issue the sector lockdown command, the cs pin must first be asserted and the opcode of 33h must be clocked into the device followed by three address bytes designating any address within the 64-kbyte sector to be locked down. after the three address bytes have been clocked in, a confirmation byte of d0h must also be clocked in immediately following the three address bytes. any additional data clocked into the device after the first byte of data will be ignored. when the cs pin is deas- serted, the sector lockdown register corresponding to the sector addressed by a23-a0 will be set to the logical ?1? state, and the sector itself will then be permanently locked down from program and erase operations within a time of t lock . in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes and the correct confirmation byte value of d0h must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operatio n. when the device aborts the sector lock down operation, the state of the corresponding sector lockdown register as well as the sle bit in the status register will be unchanged; however, the wel bit in the stat us register will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking down of sectors, the sector lockdown command can be enabled and disabled as needed by using the sle bit in the stat us register. in addition, the current sector lock- down state can be frozen so that no further modifications to the sector lockdown registers can be made (see ?freeze sector lockdown state? below). if the sector lockdown command is disabled or if the sector lockdown state is frozen, then any attempts to issue the sector lockdown command will be ignored, and th e device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. table 10-1. sector lockdown register values value sector lockdown status 0 sector is not locked down and can be progra mmed and erased. this is the default state. 1 sector is permanently locked down and can never be programmed or erased again.
26 8715b?sflsh?8/10 atmel at25df081a figure 10-1. sector lockdown 10.2 freeze sector lockdown state the current sector lockdown state can be permanently frozen so that no further modifications to the sector lock- down registers can be made; therefore, the sector lockdown command will be permanently disabled, and no additional sectors can be locked down aside from those already locked down. any attempts to issue the sector lockdown command after the sector lockd own state has been frozen will be ignored. before the freeze sector lockdown state command c an be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. in addition, the sector lockdown enabled (sle) bit in the status register must have also be en previously set to the logical ?1? state. to issue the freeze sector lockdown state command, the cs pin must first be asserted and the opcode of 34h must be clocked into the device followed by three command specific address bytes of 55aa40h. after the three address bytes have been clocked in, a confirmation byte of d0h must be clocked in immediately following the three address bytes. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the current sec- tor lockdown state will be permanen tly frozen within a time of t lock . in addition, the wel bit in the status register will be reset back to the logical ?0? state, and the sle bit will be permanently reset to a logical ?0? to indicate that the sector lockdown command is permanently disabled. the complete and correct three address bytes and the confir mation byte must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); other- wise, the device will abort the operation. when the device aborts the freeze sector lockdown state operation, the wel bit in the status register will be reset to a logical ?0?; however, the state of the sle bi t will be unchanged. figure 10-2. freeze sector lockdown state sck cs si so msb msb 23 1 0 00110011 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb 1101000 0 address bits a23-a0 confirmation byte in sck cs si so msb msb 23 1 0 00110100 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance 01 000 0 msb 1101000 0 address bits a23-a0 confirmation byte in
27 8715b?sflsh?8/10 atmel at25df081a 10.3 read sector lockdown registers the sector lockdown registers can be read to determine the current lockdown status of each physical 64-kbyte sector. to read the sector lockdown register for a particular 64-kbyte sector, the cs pin must first be asserted and the opcode of 35h must be clocked in. once the opcode has been clocked in, three address bytes designating any address within the 64-kbyte sector must be clocked in. after the add ress bytes have been clocked in, data will be output on the so pin during every subsequent clock cyc le. the data being output will be a repeating byte of either ffh or 00h to denote the value of the appropriate sector lockdown register. at clock frequencies above f clk , the first byte of da ta output will not be va lid. therefore, if operating at clock fre- quencies above f clk , at least two bytes of data must be clocked out from the device in order to determine the correct status of the appropriate sector lockdown register. deasserting the cs pin will terminate the read operation and put t he so pin into a high-im pedance stat e. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 10-3. read sector lockdown register table 10-2. read sector lockdown register ? output data output data sector lockdown register value 00h sector lockdown register value is 0 (sector is not locked down) ffh sector lockdown register value is 1 (sector is permanently locked down) sck cs si so msb msb 23 1 0 00110101 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care data byte high-impedance
28 8715b?sflsh?8/10 atmel at25df081a 10.4 program otp s ecurity register the device contains a specialized ot p (one-time programmable) security register that can be used for pur- poses such as unique device serialization, system-lev el electronic serial number (esn) storage, locked key storage, etc. the otp security register is independent of the main flash memory array and is comprised of a total of 128-bytes of memory divided into two portions. the first 64-bytes (byte locations 0 through 63) of the otp secu- rity register are allocated as a one-time user-programmable space. once these 64-bytes have been programmed, they cannot be erased or reprogrammed. the remaining 64-bytes of the otp security register (byte locations 64 through 127) are factory programmed by atmel ? and will contain a unique value fo r each device. the factory pro- grammed data is fixed and cannot be changed. the user-programmable portion of the otp security register does not need to be erased before it is programmed. in addition, the program otp security register command operates on the entire 64-byte user-programmable por- tion of the otp security register at one time. once the user-programmable space has been programmed with any number of bytes, the user-programmable space cannot be programmed again; therefore, it is not possible to only program the first two bytes of the register and then program the remaining 62-bytes at a later time. before the program otp security register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to program the otp security register, the cs pin must first be asserted and an opcode of 9bh must be clocked into the device followed by the three address bytes denoting the first byte location of the otp security register to begin programming at. since the size of the user-programmable portion of the otp security register is 64-bytes, the upper order address bits do not need to be decoded by the device. therefore, address bits a23-a6 will be ignored by the device and their values can be either a logical ?1? or ?0?. after the address by tes have been clocked in, data can then be clocked into the device and will be stored in the internal buffer. if the starting memory address denoted by a23-a0 does not start at the beginning of the otp security register memory space (a5-a0 are not all 0), then special circumstances regarding which otp security register locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the 64-byte user-programmable sp ace will wrap around back to the beginning of the otp security register. for exam- ple, if the starting address denoted by a23-a0 is 00003eh, and three bytes of data are sent to the device, then the first two bytes of data will be progra mmed at otp security register addr esses 00003eh and 00003fh while the last byte of data will be programmed at address 000000h. the remaining bytes in the otp security register (addresses 000001h through 0 0003dh) will not be pr ogrammed and will remain in the erased stat e (ffh). in addi- tion, if more than 64-bytes of data are sent to the device, then only the last 64-byt es sent will be latched into the internal buffer. when the cs pin is deasserted, the device will ta ke the data stored in the intern al buffer and program it into the appropriate otp security register locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 64-bytes of data were sent to the device, then the remaining bytes within the otp security register will not be programmed and will remain in the eras ed state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t otpp . it is not possible to suspend the pro- gramming of the otp security register. table 10-3. otp security register security register byte number 01 . . . 62 63 64 65 . . . 126 127 one-time user programmable factory programmed by atmel
29 8715b?sflsh?8/10 atmel at25df081a the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundarie s (multiples of eight bits); otherwise, the device will abort the operation and the user-programmable po rtion of the otp security register will not be pro- grammed. the wel bit in the st atus register will be reset back to the logi cal ?0? state if the otp security register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the user-programmable portion of the otp security register was previously programmed. while the device is programming the ot p security register, the status regist er can be read a nd will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t otpp time to determine if the data bytes have finished programming. at some point before the otp security register programming comple tes, the wel bit in the status register will be reset back to th e logical ?0? state. if the device is powered-down during the otp security register program cycle, then the contents of the 64-byte user programmable portion of the otp security register cannot be guaranteed and cannot be programmed again. the program otp security register command utiliz es the internal 256-buffer for pr ocessing. therefore, the con- tents of the buffer will be altered from its pr evious state when th is command is issued. figure 10-4. program otp security register sck cs si so msb msb 23 1 0 10011011 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n
30 8715b?sflsh?8/10 atmel at25df081a 10.5 read otp security register the otp security register can be sequentially read in a similar fashion to the read array operation up to the max- imum clock frequency specified by f max . to read the otp security register, the cs pin must first be asserted and the opcode of 77h must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the otp security register. following the three address bytes, two dummy bytes must be clocked into the device before data can be output. after the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in otp security register data being output on the so pin. when the last byte (00007fh) of the otp security register has been read, the device will continue reading back at th e beginning of the register (000000h). no delays will be incurred when wrapping around from the end of the register to the beginning of the register. deasserting the cs pin will terminate the read operat ion and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 10-5. read otp security register sck cs si so msb msb 23 1 0 01110111 67 5 41011 9 812 3336 35 34 31 32 29 30 opcode aaaa aaa a axx x msb msb ddddddd d d d address bits a23-a0 msb xxxxx x don't care data byte 1 high-impedance
31 8715b?sflsh?8/10 atmel at25df081a 11. status register commands 11.1 read status register the two-byte status register can be read to determine the device?s ready/busy status, as well as the status of many other functions such as hardware locking and software protection. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the cs pin must first be asserted and the opcode of 05h must be clocked into the device. after the opcode has been clock ed in, the device will begin outputting st atus register data on the so pin during every subsequent clock cycle. after the second by te of the status register has been clocked out, the sequence will repeat itself starting again with the firs t byte of the status register as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence will output new data. the rdy/bsy status is available for both bytes of the status register and is updated for each byte. at clock frequencies above f clk , the first two bytes of data output from the status register will not be valid. there- fore, if operating at clock frequencies above f clk , at least four bytes of data must be clocked out from the device in order to read the correct values of both bytes of the status register. deasserting the cs pin will terminate the read stat us register o peration and put the so pin into a high-imped- ance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. notes: 1. only bit 7 of status register byte 1 will be modified when using the write status register byte 1 command. 2. r/w = readable and writeable r = readable only table 11-1. status register format ? byte 1 bit (1) name type (2) description 7 sprl sector protection registers locked r/w 0 sector protection registers are unlocked (default) 1 sector protection registers are locked 6 res reserved for future use r 0 reserved for future use 5 epe erase/program error r 0 erase or program operation was successful 1 erase or program error detected 4 wpp write protect (wp ) pin status r 0wp is asserted 1wp is deasserted 3:2 swp software protection status r 00 all sectors are software unprotected (all sector protection registers are 0) 01 some sectors are software protected. read individual sector protection registers to determine which sectors are protected 10 reserved for future use 11 all sectors are software protected (all sector protection registers are 1 ? default) 1 wel write enable latch status r 0 device is not write enabled (default) 1 device is write enabled 0 rdy/bsy ready/busy status r 0 device is ready 1 device is busy with an internal operation
32 8715b?sflsh?8/10 atmel at25df081a notes: 1. only bits 4 and 3 of status register byte 2 will be modified when using the write status register byte 2 command. 2. r/w = readable and writeable r = readable only 11.1.1 sprl bit the sprl bit is used to control whether the sector prot ection registers can be modified or not. when the sprl bit is in the logical ?1? state, all sector protection registers are locked and cannot be modified with the protect sec- tor and unprotect sector commands (the device will ignore these commands). in add ition, the glob al protect and global unprotect features ca nnot be performed. any sector s that are presentl y protected will remain protected, and any sectors that are presently un protected will rema in unprotected. when the sprl bit is in the logical ?0? state, all sector protection registers are unlocked and can be modified (the protect sector and unpr otect sector commands, as well as the globa l protect and global unprotect features, will be processed as normal). the sprl bit defaults to the lo gical ?0? state after device power-up. the reset command has no effect on the sprl bit. the sprl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is asserted, then the sprl bit may only be changed from a logical ?0? (sec tor protection registers are unlocked) to a logical ?1? (sector protection registers are locked). in order to rese t the sprl bit back to a logical ?0? using the write status register byte 1 command, the wp pin will have to first be deasserted. the sprl bit is the only bit of status register byte 1 that can be user modified via the write status register byte 1 command. 11.1.2 epe bit the epe bit indicates whet her the last er ase or program oper ation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logical ?1? state. the epe bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or program a protected region or a locked down sector or if the wel bit is not set prior to an erase or program operation. the epe bit will be update d after every erase and program operation. table 11-2. status register format ? byte 2 bit (1) name type (2) description 7 res reserved for future use r 0 reserved for future use 6 res reserved for future use r 0 reserved for future use 5 res reserved for future use r 0 reserved for future use 4 rste reset enabled r/w 0 reset command is disabled (default) 1 reset command is enabled 3 sle sector lockdown enabled r/w 0 sector lockdown and freeze sector lockdown state commands are disabled (default) 1 sector lockdown and freeze sector lockdown state commands are enabled 2 res reserved for future use r 0 reserved for future use 1 res reserved for future use r 0 reserved for future use 0 rdy/bsy ready/busy status r 0 device is ready 1 device is busy with an internal operation
33 8715b?sflsh?8/10 atmel at25df081a 11.1.3 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 11.1.4 swp bits the swp bits provide feedback on the software protection status for the device. there are three possible combina- tions of the swp bits that indicate whether none, some, or all of the sectors have been protected using the protect sector command or the global protect feature. if the swp bits indicate that some of the sectors have been pro- tected, then the individual sector protection registers can be read with the read sector protection registers command to determine which sectors are in fact protected. 11.1.5 wel bit the wel bit indicates the current status of the internal write enable latch. when the wel bit is in the logical ?0? state, the device will not accept any byte/page program, erase, protect sector, unprotect sector, sector lock- down, freeze sector lockdown state, program otp securi ty register, or write status register commands. the wel bit defaults to the logical ?0? st ate after a device power-up or reset operation. in a ddition, the wel bit will be reset to the logical ?0? state automatically under the following conditions: ? write disable operation completes successfully ? write status register operation completes successfully or aborts ? protect sector operation completes successfully or aborts ? unprotect sector operation co mpletes successfully or aborts ? sector lockdown operation completes successfully or aborts ? freeze sector lockdown state operation completes successfully or aborts ? program otp security register operation completes successfully or aborts ? byte/page program operation completes successfully or aborts ? block erase operation completes successfully or aborts ? chip erase operation completes successfully or aborts ? hold condition aborts if the wel bit is in the logical ?1? state, it will not be reset to a lo gical ?0? if an operation a borts due to an incomplete or unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode for a byte/page program, erase, protect sector, unprotect sector, sector lockdown, freeze sector lockdown state, program otp security register, or write sta- tus register command must have been clocked into the device. 11.1.6 rste bit the rste bit is used to enable or disable the reset comm and. when the rste bit is in the logical ?0? state (the default state after power-up), the reset command is disabled and any attempts to reset the device using the reset command will be ignored. when the rste bit is in the logical ?1? state, the reset command is enabled. the rste bit will retain its state as long as power is applied to the device. once set to the logical ?1? state, the rste bit will remain in that state until it is modified using the write status register byte 2 command or until the device has been power cycled. the reset command itself will not change the state of the rste bit.
34 8715b?sflsh?8/10 atmel at25df081a 11.1.7 sle bit the sle bit is used to enable and disable the sector lockdown and freeze sector lockdown state commands. when the sle bit is in the logical ?0? state (the default state after power-up), the sector lockdown and freeze sec- tor lockdown commands are disabled. if the sect or lockdown and freeze sector lockdown commands are disabled, then any attempts to issue the commands will be i gnored. this provides a sa feguard for these commands against accidental or erroneous execution. when the sle bit is in the logical ?1? state, the sector lockdown and freeze sector lockdown state commands are enabled. unlike the wel bit, the sle bit does not automatically re set after certain device operations. therefore, once set, the sle bit will remain in the logical ?1 ? state until it is modifi ed using the write status register byte 2 command or until the device has been power cycled. the re set command has no e ffect on the sle bit. if the freeze sector lockdown state command has been issued, then the sle bit will be per manently reset in the logical ?0? state to indicate that the sector lockdown command has been disabled. 11.1.8 rdy/bsy bit the rdy/bsy bit is used to determi ne whether or not an intern al operation, such as a pr ogram or erase, is in prog- ress. to poll the rdy/bsy bit to detect the completion of a program or erase cycle, new status register data must be continually clocked out of the device until the state of the rdy/bsy bit changes from a logical ?1? to a logical ?0?. figure 11-1. read status register sck cs si so msb 23 1 0 00000101 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 28 29 27 26 25 30 opcode msb msb dddddd d d d d msb ddddd d d d dd d d d d status register byte 1 status register byte 1 status register byte 2 high-impedance
35 8715b?sflsh?8/10 atmel at25df081a 11.2 write status register byte 1 the write status register byte 1 command is used to modi fy the sprl bit of the status register and/or to perform a global protect or global unprotect operation. before the write status register byte 1 command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register byte 1 command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. the one byte of data consists of the sprl bit value, a don?t care bit, four data bits to denote whether a glo bal protect or unprotect should be performed, and two addi- tional don?t care bits (see table 11-3 ). any additional data bytes that are sent to the device will be ignored. when the cs pin is deasserted, the sprl bit in the status regist er will be modified, an d the wel bit in the status regis- ter will be reset back to a logical ?0?. the values of bits five, four, three, and two and the state of the sprl bit before the write status register byte 1 command was executed (the prior state of the sprl bit) will determine whether or not a global protect or global unprotect will be performed. pl ease refer to ?global protect/unprotect? on page 21 for more details. the complete one byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte bound aries (multiples of eight bits); otherwise, the devi ce will abort the operation, the state of the sprl bit will not chang e, no potential global pr otect or unprotect will be performed, and the wel bit in the status register will be re set back to the logical ?0? state. if the wp pin is asserted, then the sprl bit can only be set to a logical ?1?. if an attempt is made to reset the sprl bit to a logical ?0? while the wp pin is asserted, then the write status register byte 1 comm and will be ignored, and the wel bit in the status register will be reset back to the l ogical ?0? state. in order to reset the sprl bit to a logi- cal ?0?, the wp pin must be deasserted. figure 11-2. write status register byte 1 table 11-3. write status register byte 1 format bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sprl x global protect/unprotect x x sck cs si so msb 23 1 0 0000000 67 5 4 opcode 10 11 9 81415 13 12 1 msb dxdddd x x status register in byte 1 high-impedance
36 8715b?sflsh?8/10 atmel at25df081a 11.3 write status register byte 2 the write status register byte 2 command is used to modify the rste and sle bits of the status register. using the write status register byte 2 command is the only way to modify the rste and sle bits in the status register during normal device operation, and the sle bit can only be modified if the sector lockdown state has not been fro- zen. before the write status register byte 2 command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register byte 2 command, the cs pin must first be asserted and the opcode of 31h must be clocked into the device followed by one byte of data. th e one byte of data consists of three don?t care bits, the rste bit value, the sle bit value, and three additional don?t care bits (see table 11-4 ). any additional data bytes that are sent to the device will be ignored. when the cs pin is deasserted, the rste and sle bits in the status register will be modified, and the wel bi t in the status register will be reset back to a logical ?0?. the sle bit will only be modified if the freeze sector lockdown state command has not been previously issued. the complete one byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundar ies (multiples of eight bits); otherwis e, the device will abort the operation, the state of the rste and sle bits will not change, and the wel bit in the status register will be reset back to the logical ?0? state. figure 11-3. write status register byte 2 table 11-4. write status register byte 2 format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxrsteslexxx sck cs si so msb 23 1 0 0011000 67 5 4 opcode 10 11 9 81415 13 12 1 msb xxxddx x x status register in byte 2 high-impedance
37 8715b?sflsh?8/10 atmel at25df081a 12. other commands and functions 12.1 reset in some applications, it may be nece ssary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or millis econds necessary for the program or erase operatio n to complete normally. the reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state. since the need to reset the device is immediate, the write enable command does not need to be issued prior to the reset command being issued. therefore, the reset command operates independently of the state of the wel bit in the status register. the reset command can only be executed if the command has been enabled by setting the reset enabled (rste) bit in the status register to a logical ?1?. if the reset command has not been enabled (the rste bit is in the logical ?0? state), then any attempts at executing th e reset command will be ignored. to perform a reset, the cs pin must first be asserted and the opcode of f0h must be clocked into the device. no address bytes need to be clocked in, but a confirmation byte of d0h must be clocked in to the device immediately after the opcode. any additional data clocked into the device after the c onfirmation byte will be ignored. when the cs pin is deasserted, the program or er ase operation currently in progress will be terminated within a time of t rst . since the program or erase operation may not complete before the device is reset, the contents of the page being programmed or the block being erased cannot be guaranteed to be valid. the reset command has no effect on the states of the sector protection registers, the sector lockdown regis- ters, or the sprl, rste, and sle bits in the status r egister. the wel, ps, and es bits, however, will be reset back to their default states. the complete opcode and confirmation byte must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no reset operation will be performed. figure 12-1. reset sck cs si so msb 23 1 0 1111000 67 5 4 opcode confirmation byte in 10 11 9 81415 13 12 0 msb 110100 0 0 high-impedance
38 8715b?sflsh?8/10 atmel at25df081a 12.2 read manufacturer and device id identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor spe- cific device id, and the vendor spec ific extended device information. the read manufacturer and device id command is limited to a maximum clock frequency of f clk . since not all flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably lo w clock frequency to ensure that all devices to be used in the application can be identified properly. once the iden tification process is complete, the application can then increase the clock frequency to accommo date specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the iden tification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fo urth byte output will be the extended device informat ion string length, which will be 00h indicating that no extended device information follows. after t he extended device information string length byte is output, the so pin will go into a high-impedance st ate; therefore, additional clock cycles will have no affect on the so pin and no data will be outp ut. as indicated in the jedec sta ndard, reading the extended device information string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 12-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 45h 3 device id (part 2) 01h 4 [optional to read] extended device information (edi) string length 01h 5 [optional to read] edi byte 1 00h table 12-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for atmel) 00011111 device id (part 1) family code density code 45h family code: 010 (at25df/26dfxxx series) density code: 00101 (8-mbit) 01000101 device id (part 2) sub code product version code 01h sub code: 000 (standard series) product version: 00001 (s econd major version) 00000001
39 8715b?sflsh?8/10 atmel at25df081a figure 12-2. read manufacturer and device id 12.3 deep power-down during normal operation, the device w ill be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-do wn command offers the ability to place the device into an even lower power consumption state called the deep power-down mode. when the device is in the deep power-down mode, all co mmands including the read status register command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise , the device will abort the operation and return to the standby mode once the cs pin is deasserted. in additi on, the device will default to the standby mode after a power- cycle. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. 6&. &6 6, 62 )k )k k k k k +,*+,03('$1&( opcode manufactured id device id byte 1 device id byte 2 edi s tring length edi data byte 1 note: e a ch tr a n s ition s hown for s i a nd s o repre s ent s one b yte ( 8 b it s )
40 8715b?sflsh?8/10 atmel at25df081a figure 12-3. deep power-down 12.4 resume from deep power-down in order to exit the deep power-down mode and resume normal device operation, the resume from deep power- down command must be issued. the resume from deep power-down command is the only command that the device will recognized while in the deep power-down mode. to resume from the deep power-down mode, the cs pin must first be asserted and opcode of abh must be clocked into the device . any additional data clocked into the device after the opc ode will be ignored. when the cs pin is deasserted, the device will exit the deep power-down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, or if the cs pin is not deasserted on an even byte boundary (multiples of eigh t bits), then the device will abort the o peration and return to the deep power- down mode. figure 12-4. resume from de ep power-down sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
41 8715b?sflsh?8/10 atmel at25df081a 12.5 hold the hold pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a pro- gram or erase cycle. therefore, if an erase cycle is in progress, asserting the hold pin will not pause the operation, and the er ase cycle will continue until it is finished. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won?t be started until the beginning of the next sck lo w pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pin will be in a high-impedance stat e. in addition, both th e si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the hold pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, th en the hold mode won?t end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still asserted, th en any operation that may have been started will be aborted, and t he device will reset the wel bit in the status register back to the logical ?0? state. figure 12-5. hold mode sck cs hold hold hold hold
42 8715b?sflsh?8/10 atmel at25df081a 13. atmel rapids implementation to implement atmel rapids tm and operate at clock frequencies higher than what can be achieved in a viable spi implementation, a full clock cycle can be used to transmit data back and forth across the serial bus. the atmel at25df081a is designed to always cloc k its data out on the falling edge of the sck signal and clock data in on the rising edge of sck. for full clock cycle operation to be achieved, when the at25df081a is cl ocking data out on the falling edge of sck, the host controller should wait until the next falling edge of sck to latch the data in. similarly, the host con- troller should clock its data out on the rising edge of sck in order to give the at25df081a a full clock cycle to latch the incoming data in on the next rising edge of sck. implementing rapids allows a system to run at higher cl ock frequencies since a full clock cycle is used to accom- modate a device?s clock-to-output time, input setup time, and associated rise/fall times. for example, if the system clock frequency is 100 mhz (10ns cycle time) with a 50% duty cycle, and the host controller has an input setup time of 2ns, then a standard spi implementation would requ ire that the slave device be capable of outputting its data in less than 3ns to meet the 2ns host controller se tup time [(10ns x 50%) ? 2ns] not accounting for rise/fall times. in an spi mode 0 or 3 implementation, the spi master is designed to clock in data on the next immediate ris- ing edge of sck after the spi slave has clocked its data out on the preceding falling edge. this essentially makes spi a half-clock cycle protocol and requires extremely fast clock-to-output times and input setup times in order to run at high clock frequencies. with a rapids implementation of this example, however, the full 10ns cycle time is available which gives the slav e device up to 8ns, not accounting for rise/fa ll times, to clock its data out. likewise, with rapids, the host controller has more time available to output its data to the slave since the slave device would be clocking that data in a full clock cycle later. figure 13-1. atmel rapids operation sck mosi miso t v 1 234567 81 234567 8 mosi = master out, slave in miso = master in, slave out the master is the asic/mcu and the slave is the memory device the master always clocks data out on the rising edge of sck and always clocks data in on the falling edge of sck the slave always clocks data out on the falling edge of sck and always clocks data in on the rising edge of sck a. master clocks out first bit of byte a on the rising edge of sck b. slave clocks in first bit of byte a on the next rising edge of sck c. master clocks out second bit of byte a on the same rising edge of sck d. last bit of byte a is clocked out from the master e. last bit of byte a is clocked into the slave f. slave clocks out first bit of byte b g. master clocks in first bit of byte b h. slave clocks out second bit of byte b i. master clocks in last bit of byte b a b c d e f g 1 h byte a msb lsb byte b msb lsb slave cs i
43 8715b?sflsh?8/10 atmel at25df081a 14. electrical specifications 14.1 absolute maximum ratings* 14.2 dc and ac operating range 14.3 dc characteristics temperature under bias .......... ..............-55 c to +125c *notice: stresses beyond those listed under ?abso- lute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. storage temperature.............................-65c to +150c all input voltages (including nc pins) with respect to ground........... ................. -0.6v to +4.1v all output voltages with respect to ground.................... -0.6v to v cc + 0.5v atmel at25df081a operating temperature (case) ind. -40c to 85c v cc power supply 2.7v to 3.6v symbol parameter condition min typ max units i sb standby current cs , wp , hold = v cc , all inputs at cmos levels 25 50 a i dpd deep power-down current cs , wp , hold = v cc , all inputs at cmos levels 510a i cc1 active current, read operation f = 100mhz; i out = 0ma; cs = v il , v cc = max 17 20 ma f = 85mhz; i out = 0ma; cs = v il , v cc = max 16 19 f = 66mhz; i out = 0ma; cs = v il , v cc = max 15 18 f = 50mhz; i out = 0ma; cs = v il , v cc = max 14 17 f = 33mhz; i out = 0ma; cs = v il , v cc = max 13 16 f = 20mhz; i out = 0ma; cs = v il , v cc = max 12 15 i cc2 active current, program operation cs = v cc , v cc = max 10 15 ma i cc3 active current, erase operation cs = v cc , v cc = max 12 18 ma i li input leakage current v in = cmos levels 1a i lo output leakage current v out = cmos levels 1a v il input low voltage 0.3 x v cc v v ih input high voltage 0.7 x v cc v v ol output low voltage i ol = 1.6ma; v cc = min 0.4 v v oh output high voltage i oh = -100a; v cc = min v cc - 0.2v v
44 8715b?sflsh?8/10 atmel at25df081a 14.4 ac characteristics ? maximum clock frequencies 14.5 ac characteristics ? all other parameters notes: 1. not 100% tested (value guaranteed by design and characterization) 2. 15pf load at frequencies above 70mhz, 30pf otherwise 3. only applicable as a constraint for the writ e status register byte 1 command when sprl = 1 symbol parameter min max units atmel rapids and spi operation f max maximum clock frequency for all operations ? rapids operation only (excluding 0bh, 03h, 3bh, and 9f opcodes) 100 mhz f clk maximum clock frequency for all operations (excluding 03h and 3bh opcodes) 85 mhz f rdlf maximum clock frequency for 03h opcode (read array ? low frequency) 50 mhz f rddo maximum clock frequency for 3bh opcode (dual-output read) 85 mhz symbol parameter min max units t clkh clock high time 4.3 ns t clkl clock low time 4.3 ns t clkr (1) clock rise time, peak-to-peak (slew rate) 0.1 v/ns t clkf (1) clock fall time, peak-to-peak (slew rate) 0.1 v/ns t csh chip select high time 50 ns t csls chip select low setup time (relative to clock) 5 ns t cslh chip select low hold time (relative to clock) 5 ns t cshs chip select high setup time (relative to clock) 5 ns t cshh chip select high hold time (relative to clock) 5 ns t ds data in setup time 2 ns t dh data in hold time 1 ns t dis (1) output disable time 5ns t v (2) output valid time 5ns t oh output hold time 2 ns t hls hold low setup time (relative to clock) 5 ns t hlh hold low hold time (relative to clock) 5 ns t hhs hold high setup time (relative to clock) 5 ns t hhh hold high hold time (relative to clock) 5 ns t hlqz (1) hold low to output high-z 5 ns t hhqx (1) hold high to output low-z 5 ns t wps (1)(3) write protect setup time 20 ns t wph (1)(3) write protect hold time 100 ns t secp (1) sector protect time (from chip select high) 20 ns t secup (1) sector unprotect time (from chip select high) 20 ns t lock (1) sector lockdown and freeze sector lockdown state time (from chip select high) 200 s t edpd (1) chip select high to deep power-down 1 s t rdpd (1) chip select high to standby mode 30 s t rst reset time 30 s
45 8715b?sflsh?8/10 atmel at25df081a 14.6 program and erase characteristics notes: 1. maximum values indicate worst-case performance after 100,000 erase/program cycles 2. not 100% tested (value guaranteed by design and characterization) 14.7 power-up conditions 14.8 input test waveforms and measurement levels 14.9 output test load symbol parameter min typ max units t pp (1) page program time (256-bytes) 1.0 3.0 ms t bp byte program time 7 s t blke (1) block erase time 4-kbytes 50 200 ms 32-kbytes 250 600 64-kbytes 400 950 t chpe (1)(2) chip erase time 16 28 sec t otpp (1) otp security register program time 200 500 s t wrsr (2) write status register time 200 ns symbol parameter min max units t vcsl minimum v cc to chip select low time 100 s t puw power-up device delay before program or erase allowed 10 ms v por power-on reset voltage 1.5 2.5 v ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2 ns (10% to 90%) device under te s t 15pf (fre qu encie s ab ove 70mhz) or 3 0pf
46 8715b?sflsh?8/10 atmel at25df081a 15. ac waveforms figure 15-1. serial input timing figure 15-2. serial output timing figure 15-3. wp timing for write status register byte 1 command when sprl = 1 cs si sck so msb high-impedance msb lsb t csls t clkh t clkl t cshs t cshh t ds t dh t cslh t csh cs si sck so t v t clkh t clkl t dis t v t oh wp si sck so 00 0 high-impedance msb x t wps t wph cs lsb of write status register data byte msb of write status register byte 1 opcode msb of next opcode
47 8715b?sflsh?8/10 atmel at25df081a figure 15-4. hold timing ? serial input figure 15-5. hold timing ? serial output cs si sck so t hhh t hls t hlh t hhs hold high-impedance cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx
48 8715b?sflsh?8/10 atmel at25df081a 16. ordering information 16.1 code detail detail 16.2 green package options (pb/ halide-free/rohs compliant) note: the shipping carrier option code is not marked on the devices. atmel de s i g nator product family device den s ity interface s hippin g carrier option device grade packa g e option 1 = s eri a l 8 = 8 -meg ab it b = b u lk (t ub e s ) y = b u lk (tr a y s ) t = t a pe a nd reel h = green, nipda u le a d fini s h, ind us tri a l temper a t u re r a nge (-40c to + 8 5c) ss = 8 -le a d, 0.150" wide s oic s = 8 -le a d, 0.20 8 " wide s oic m = 8 -p a d, 5 x 6 x 0.6mm udfn at25df0 8 1a- ss h-b ordering code package lead (pad) finish operating voltage max. freq. (mhz) operation range at25df081a-mh-y AT25DF081A-MH-T 8ma1 nipdau 2.7v to 3.6v 100 industrial (-40c to +85c) at25df081a-ssh-b at25df081a-ssh-t 8s1 at25df081a-sh-b at25df081a-sh-t 8s2 package type 8ma1 8-pad (5 x 6 x 0.6 mm body), thermally enhanced pl astic ultra thin dual flat no lead package (udfn) 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.208? wide, plastic gull wing small outline package (eiaj soic)
49 8715b?sflsh?8/10 atmel at25df081a 17. packaging information 17.1 8ma1 ? udfn packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com drawing no. rev. title gpc note s : 1. thi s p a ck a ge conform s to jedec reference mo-229, sa w s ing u l a tion. 2. the termin a l #1 id i s a l as er-m a rked fe a t u re. 8 ma1 d 4/15/0 8 8 ma1, 8 -p a d (5 x 6 x 0.6mm body), therm a lly enh a nced pl as tic ultr a thin d ua l fl a t no le a d p a ck a ge (udfn) yfg top view s ide view common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note 0.45 0.00 0. 3 5 4.90 3 . 8 0 5.90 3 .20 0.50 0.00 0.20 a a1 b c d d2 e e2 e l y k 0.55 0.02 0.40 0.152 ref 5.00 4.00 6.00 3 .40 1.27 0.60 ? ? 0.60 0.05 0.4 8 5.10 4.20 6.10 3 .60 0.75 0.0 8 ? pin 1 id e d a1 a y c bottom view e2 d2 l b e 1 2 3 4 8 7 6 5 pin #1 notch (0.20 r) k pin #1 ch a mfer (c 0. 3 5) option a (option b)
50 8715b?sflsh?8/10 atmel at25df081a 17.2 8s1 ? jedec soic packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com drawing no. rev. title gpc common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a1 0.10 ? 0.25 a 1. 3 5 ? 1.75 b 0. 3 1 ? 0.51 c 0.17 ? 0.25 d 4. 8 0 ? 5.05 e1 3 . 8 1 ? 3 .99 e 5.79 ? 6.20 e 1.27 b s c l 0.40 ? 1.27 ? ? 0 ? 8 ? ? e e 1 1 n n top view t o p v i e w c c e1 e 1 end view a a b b l l a1 a 1 e e d d s ide view s i d e v i e w 8s 1f 5/19/10 note s : thi s dr a wing i s for gener a l inform a tion only. refer to jedec dr a wing m s -012, v a ri a tion aa for proper dimen s ion s , toler a nce s , d a t u m s , etc. 8s 1, 8 -lead (0.150? wide body), pla s tic gull wing s m a ll o u tline (jedec s oic) s wb
51 8715b?sflsh?8/10 atmel at25df081a 17.3 8s2 ? eiaj soic packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com drawing no. rev. title gpc 1 1 n n e e q q c c e1 e 1 l l a a b b a1 a 1 e e d d note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to eiaj dr a wing edr-7 3 20 for a ddition a l inform a tion. 2. mi s m a tch of the u pper a nd lower die s a nd re s in bu rr s a re not incl u ded. 3 . determine s the tr u e geometric po s ition. 4. v a l u e s b , c a pply to pl a ted termin a l. the s t a nd a rd thickne ss of the pl a ting l a yer s h a ll me asu re b etween 0.007 to .021mm. 8s 2f 4/15/0 8 8s 2 , 8 -le a d, 0.20 8? body, pl as tic s m a ll o u tline p a ck a ge (eiaj) s tn end view top view s ide view common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note 1.70 0.05 0. 3 5 0.15 5.1 3 5.1 8 7.70 0.51 0? a a1 b c d e1 e l q e 1.27 b s c 2.16 0.25 0.4 8 0. 3 5 5. 3 5 5.40 8 .26 0. 8 5 8 ? 4 4 2 3
52 8715b?sflsh?8/10 atmel at25df081a 18. revision history doc. rev. date comments 8715b 08/2010 change t rdpd max from 10 to 30 in ac parameters 8715a 06/2010 initial document release
8715b?sflsh?8/10 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel europe atmel munich gmbh business campus, parkring 4 d-85748 garching bei munich germany tel: (+49) 89-31970-0 fax: (+49) 89-31946-21 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81) 3-3523-3551 fax: (+81) 3-3523-7581 product contact web site www.atmel.com technical support dataflash@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2010 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, dataflash ? , rapids, and others are registered trademarks or trademarks of atmel corporation or its subsidia ries. other terms and product names may be trademarks of others.

▲Up To Search▲

Price & Availability of AT25DF081A-MH-T

	To Download AT25DF081A-MH-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .